Power management apparatus with rapid short response and full load recovery

ABSTRACT

A voltage feedback loop employed with a power distribution switch rapidly responds to a predetermined drop in output voltage to increase the resistance of the switch for a predetermined time. After this predetermined time, a current feedback loop controls the resistance until the output voltage recovers, while also isolating the voltage feedback loop from the switch.

FIELD

The present work relates generally to power distribution switches and,more particularly, to hard short response in a power distributionswitch.

BACKGROUND

Power distribution switches are used in power management integratedcircuits to distribute power to subsystems. In one example, powerdistribution switches are used to limit the current flowing to an outputdevice. For example, in a computer system a power distribution switchmay couple a power source to an output terminal, thereby supplying powerto an attached device. Some devices are limited to 0.5 amperes (A) ofcurrent for extended periods, but the devices may occasionally draw morecurrent than this limit. If a device overdraws current for too long, thepower distribution switch may increase its resistance, thereby reducingthe current draw and preventing the device from significantly affectingthe voltage level of the power source.

Conventional power distribution switches include analog feedback loopsto monitor the input to the power distribution switch for excessivecurrent draw by a device drawing power from the output. In an example, asense resistor is placed in series with the current supply to generate asense voltage that is compared to a desired reference voltage at anamplifier. In such arrangements, the output of the amplifier controlsthe power distribution switch coupling the power source to the outputterminal, and increases the resistance of the switch if the sensevoltage indicates that too much current is being drawn. However, in thecase of a hard short circuit condition (e.g., a condition in which theresistance between an output terminal of the power distribution switchand ground drops to roughly 0.1 ohms), large currents may flow throughthe power distribution switch before the feedback loop can respond toincrease resistance of the power distribution switch. This condition maybe damaging to the power distribution switch, or may lead to a situationin which the power source voltage is pulled below tolerable levels.

One conventional approach, described in U.S. Pat. No. 7,817,393(incorporated by reference herein in its entirety), addresses theundesired slow response to hard short by adding a digital voltagefeedback loop that responds to the hard short more rapidly than theanalog feedback loop. In response to detection of a hard short, thedigital loop disables, and/or increases the resistance of, one or moreconduction paths in the power distribution switch, thereby increasingits series resistance. For example, if the current limit of the switchis set to 1 A, the digital loop may rapidly disable ⅘ of the conductionpaths, thereby limiting the current to 200 mA. This condition persistsuntil the output terminal voltage recovers from the hard short. However,in some situations, the load device attached to the output terminal mayrequire full current (e.g., significantly more than 200 mA) for startup, such that the output terminal voltage cannot recover while the 200mA current limit condition persists.

It is desirable in view of the foregoing to provide for rapid currentlimit protection against shorts without requiring the output terminalvoltage to recover before the current limit condition can be removed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 diagrammatically illustrates a system including a powermanagement apparatus according to example embodiments of the presentwork.

DETAILED DESCRIPTION

Example embodiments of the present work provide a power managementapparatus having a voltage feedback loop that rapidly responds to apredetermined drop in output voltage to increase the resistance of apower distribution switch for a predetermined time, after which acurrent feedback loop controls the resistance until the output voltagerecovers, while also isolating the voltage feedback loop from theswitch. The current limit condition imposed by the voltage feedback looptherefore does not persist until the output voltage recovers, incontrast to the aforementioned prior art arrangement. Rather, thecurrent feedback loop regulates the switch current back to a full loadcondition, which permits the output voltage to recover at full currentload, in contrast to the prior art.

FIG. 1 diagrammatically illustrates a system (e.g., a computer system)including a power management apparatus 5 coupled to a load apparatus 21(e.g., a computer apparatus) according to example embodiments of thepresent work. The power management apparatus 5 includes a powerdistribution switch (switching device) 11 that provides a seriesresistance between a power source terminal 12 at an input voltage Vinand an output terminal 13 at an output voltage Vout. As shown in FIG. 1,the switching device 11 is, in some embodiments, an FET whose drain andsource are respectively coupled to the power source terminal 12 and theoutput terminal 13, and whose gate 10 is coupled, via a resistanceRpull, to an output voltage (Vpump) of a charge pump. Such arrangementof a power distribution switch is known in the art.

The power management apparatus 5 further includes a current feedbackloop that monitors current through the switching device 11. The currentfeedback loop includes a voltage comparator 14 having a positive inputheld at a reference voltage level Ref that is generated in conventionalfashion by a reference current source Iref and a reference resistance(realized by a sense FET in FIG. 1) connected between the power sourceterminal 12 and the reference current source Iref. A negative input ofcomparator 14 receives a sense voltage level Sense that corresponds tothe current through switching device 11. The Sense voltage is obtainedin conventional fashion from a sense resistance R connected between thepower source terminal 12 and the switching device 11. The currentfeedback loop thus monitors the switch current (current throughswitching device 11) relative to the reference current Iref inconventional fashion.

The output of comparator 14 controls the gate of an FET switch 20 whosesource is grounded and whose drain is connected to the gate 10 ofswitching device 11. If the switch current increases beyond a limit setby Iref (such as would occur if the output terminal 13 is shorted toground), the voltage Sense drops below the voltage Ref, driving theoutput of comparator 14 active high to turn on the switch 20 and pulldown the gate 10 of switching device 11. This increases the resistancepresented by switching device 11, thereby limiting the switch current.Under tolerable switch current conditions, the output of comparator 14remains inactive low, keeping the switch 20 off.

The power management apparatus 5 further includes a voltage feedbackloop (Fast Voltage Loop) that monitors the output voltage Vout. Thevoltage feedback loop includes a voltage comparator 15 that comparesVout, at its negative input, with a reference voltage at its positiveinput that is a predetermined fraction of the input voltage Vin. Inconventional fashion, a resistor voltage divider 16 sets the referencevoltage for the positive input of comparator 15. An RC filter isprovided between the divider 16 and the comparator 15, as is alsoconventional. As is known in the art, this conventional output voltagemonitoring responds to a hard short condition at the output terminal 13more rapidly than the conventional current monitoring performed by theabove-described current feedback loop.

The output of comparator 15 drives the clock input of a DQ flip-flop 17whose D input is held at logic 1. The Q output drives an input of ANDgate 19, whose other input is driven by the inverted output of thecomparator 14. The inverted Q output, designated Qb, is fed back,through an RC delay loop 18 that includes an AND gate 22, to control theclear input CLRz of the flip-flop 17. This feedback-delay loop 18permits the flip-flop to clear itself, as described in more detailbelow.

When the output voltage Vout falls below the reference voltage levelprovided by voltage divider 16 (e.g., below 85% of Vin in someembodiments), the output of comparator 15 goes high, and clocks logic 1to the Q output of flip-flop 17. With the output of comparator 14 (inthe slower current feedback loop) still low, the Q output is qualifiedat AND gate 19, taking the gate of FET switch Mfast high. The switchMfast is connected in parallel with aforementioned switch 20. When thegate of Mfast goes high, this pulls down the voltage on the gate 10 ofswitching device 11, thereby increasing its resistance to limit thecurrent. The feedback-delay loop 18 ensures that the Q output offlip-flop 17 is high for only a limited time, which is determined by theRC time constant of the loop. The low output from Qb is delayed due tothe RC time constant of loop 18, and then, if qualified by signal EN atAND gate 22, clears the flip-flop 17 via AND gate 22 and the (activelow) CLRz input of the flip-flop. Thus, the flip-flop 17 andfeedback-delay loop 18 form a digital pulse generator, and the Q outputprovides a digital pulse whose width is determined by the RC timeconstant of loop 18. In various example embodiments, the pulse width hasvarious values in a range of 2-20 microseconds.

When digital the pulse ends, the switch Mfast turns off, so currentlimiting by the voltage feedback loop ends. From this point, the gate 10of the switching device 11 is controlled by comparator 14 via switch 20as described above. While the output of comparator 14 is activelyregulating current through switching device 11 via switch 20, the Qoutput of flip-flop 17 is isolated from switch Mfast (via AND gate 19).The voltage feedback loop cannot affect the switching device 11 againuntil the output voltage Vout recovers, which causes the output ofcomparator 14 to re-assume its inactive low state.

Although example embodiments of the present work have been describedabove in detail, this does not limit the scope of the work, which can bepracticed in a variety of embodiments.

What is claimed is:
 1. A power management apparatus, comprising: aswitching device that provides a resistance between a power sourceterminal and an output terminal, said power source terminal having aninput voltage, and said output terminal having an output voltage; and avoltage feedback loop coupled to said switching device and said outputterminal, said voltage feedback loop configured to monitor said outputvoltage and selectively control said switching device based on saidoutput voltage to increase said resistance for a predetermined timeduration, wherein said voltage feedback loop is configured toselectively generate a digital pulse of said predetermined time durationbased on said output voltage, and wherein said resistance increases inresponse to said digital pulse.
 2. The apparatus of claim 1, whereinsaid voltage feedback loop includes a voltage comparator that monitorssaid output voltage relative to said input voltage, and a pulsegenerator coupled to said voltage comparator for generating said digitalpulse in response to a predetermined decrease in said output voltagerelative to said input voltage.
 3. The apparatus of claim 2, whereinsaid pulse generator includes a flip-flop and a delay loop coupled tosaid flip-flop.
 4. The apparatus of claim 1, including a currentfeedback loop coupled to said power source terminal and said switchingdevice, said current feedback loop configured to monitor a currentthrough said switching device and selectively adjust said resistancebased on said current.
 5. The apparatus of claim 4, wherein said voltagefeedback loop generates said digital pulse in response to a short atsaid output terminal, and wherein, after said predetermined timeduration of said digital pulse, said current feedback loop controls saidresistance until said output voltage recovers from said short while alsokeeping said voltage feedback loop isolated from said switching device.6. The apparatus of claim 5, including logic coupled to said voltagefeedback loop and said current feedback loop and said switching devicefor permitting said current feedback loop to isolate said voltagefeedback loop from said switching device.
 7. The apparatus of claim 5,including a first switch coupled to said current feedback loop and acontrol input of said switching device, and a second switch coupled tosaid voltage feedback loop and said control input of said switchingdevice, wherein said first and second switches are connected in parallelwith one another, and wherein said first and second switches haverespective control inputs that are respectively coupled to said currentfeedback loop and said voltage feedback loop.
 8. The apparatus of claim7, wherein said voltage feedback loop includes a voltage comparator thatmonitors said output voltage relative to said input voltage, and a pulsegenerator coupled to said voltage comparator for generating said digitalpulse in response to a predetermined decrease in said output voltagerelative to said input voltage, and wherein said pulse generator iscoupled to said control input of said second switch to permit saiddigital pulse to increase said resistance by controlling said secondswitch.
 9. The apparatus of claim 7, including logic coupled betweensaid voltage feedback loop and said control input of said second switch,wherein said current feedback loop is coupled to said logic andselectively controls said logic to isolate said voltage feedback loopfrom said second switch.
 10. The apparatus of claim 5, wherein saidvoltage feedback loop includes a voltage comparator that monitors saidoutput voltage relative to said input voltage, and a pulse generatorcoupled to said voltage comparator for generating said digital pulse inresponse to a predetermined decrease in said output voltage relative tosaid input voltage.
 11. A power management apparatus, comprising: aswitching device that provides a resistance between a power sourceterminal and an output terminal, said power source terminal having aninput voltage, and said output terminal having an output voltage; firstand second switches coupled to a control input of said switching deviceand connected in parallel with one another; a voltage feedback loopcoupled to said output terminal and configured to monitor said outputvoltage, said voltage feedback loop coupled to a control input of saidfirst switch to permit said voltage feedback loop to selectively adjustsaid resistance by controlling said first switch based on said outputvoltage; and a current feedback loop coupled to said power sourceterminal and configured to monitor a current through said switchingdevice, said current feedback loop coupled to a control input of saidsecond switch to permit said current feedback loop to selectively adjustsaid resistance by controlling said second switch based on said current.12. The apparatus of claim 11, wherein said voltage feedback loop isconfigured to selectively apply a digital pulse of predetermined timeduration to said control input of said first switch based on said outputvoltage, and wherein said resistance increases in response to saidpulse.
 13. The apparatus of claim 12, wherein said voltage feedback loopgenerates said digital pulse in response to a short at said outputterminal, and wherein, after said predetermined time duration of saiddigital pulse, said current feedback loop controls said resistance untilsaid output voltage recovers from said short while also keeping saidvoltage feedback loop isolated from said switching device.
 14. Theapparatus of claim 13, including logic coupled to said current feedbackloop and said voltage feedback loop and said control input of said firstswitch for permitting said current feedback loop to isolate said voltagefeedback loop from said first switch.
 15. A power management apparatus,comprising: a switching device that provides a resistance between apower source terminal and an output terminal, said power source terminalhaving an input voltage, and said output terminal having an outputvoltage; a voltage feedback loop coupled to said output terminal andconfigured to monitor said output voltage, said voltage feedback loopcoupled to said switching device and configured to selectively adjustsaid resistance based on said output voltage; a current feedback loopcoupled to said power source terminal and configured to monitor acurrent through said switching device, said current feedback loopcoupled to said switching device and configured to selectively adjustsaid resistance based on said current; and logic coupled to said currentfeedback loop, said voltage feedback loop and said switching device,wherein said current feedback loop is configured to selectively isolatesaid voltage feedback loop from said switching device by controllingsaid logic.
 16. The apparatus of claim 15, wherein said voltage feedbackloop is configured to selectively generate a digital pulse ofpredetermined time duration based on said output voltage, and whereinsaid resistance increases in response to said digital pulse.
 17. A powermanagement apparatus, comprising: a switching device that provides aresistance between a power source terminal and an output terminal, saidpower source terminal having an input voltage, and said output terminalhaving an output voltage; first and second switches coupled to a controlinput of said switching device and connected in parallel with oneanother; a voltage feedback loop coupled to said output terminal andconfigured to monitor said output voltage, said voltage feedback loopcoupled to a control input of said first switch to permit said voltagefeedback loop to selectively adjust said resistance by controlling saidfirst switch based on said output voltage; a current feedback loopcoupled to said power source terminal and configured to monitor acurrent through said switching device, said current feedback loopcoupled to a control input of said second switch to permit said currentfeedback loop to selectively adjust said resistance by controlling saidsecond switch based on said current; wherein said voltage feedback loopis configured to selectively apply a digital pulse of predetermined timeduration to said control input of said first switch based on said outputvoltage, and wherein said resistance increases in response to saidpulse; wherein said voltage feedback loop generates said digital pulsein response to a short at said output terminal, and wherein, after saidpredetermined time duration of said digital pulse, said current feedbackloop controls said resistance until said output voltage recovers fromsaid short while also keeping said voltage feedback loop isolated fromsaid switching device; wherein said current feedback loop includes afirst comparator that receives a sense voltage input corresponding tosaid current, and a reference voltage input corresponding to a referencecurrent, and wherein said first comparator has an output coupled to saidcontrol input of said second switch; wherein said voltage feedback loopincludes a second comparator having one input that receives said outputvoltage, another input that receives a reference voltage, and an output,a flip-flop having a clock input, a clear input, a data output and aninverted data output, said clock input coupled to said output of saidsecond comparator, and a delay loop coupled between said inverted dataoutput and said clear input, wherein said delay loop provides a delaythat corresponds to said predetermined time duration; and an AND gatehaving one input coupled to said data output, another input thatreceives an inversion of said first comparator output, and having anoutput coupled to said control input of said first switch.
 18. A system,comprising: a power management apparatus including a switching devicethat provides a resistance between a power source terminal and an outputterminal, said power source terminal having an input voltage, and saidoutput terminal having an output voltage, a voltage feedback loopcoupled to said switching device and said output terminal, said voltagefeedback loop configured to monitor said output voltage and selectivelycontrol said switching device based on said output voltage to increasesaid resistance for a predetermined time duration; wherein said voltagefeedback loop is configured to selectively generate a digital pulse ofsaid predetermined time duration based on said output voltage, andwherein said resistance increases in response to said digital pulse, anda load apparatus coupled to said output terminal to receive current viasaid switch device.
 19. The system of claim 18, wherein said loadapparatus is a computer apparatus.